Semiconductor device structures including metal silicide interconnects and dielectric layers at substantially the same fabrication level

ABSTRACT

A semiconductor device includes a metal silicide interconnect structure and a dielectric layer that are located at substantially the same fabrication level. The metal silicide interconnect and dielectric layer may be fabricated by forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon layer, removing a portion of the silicon nitride layer, oxidizing the exposed portion of the silicon layer, removing the remaining portion of the silicon nitride layer, optionally removing the oxidized silicon layer, forming a metal layer over the resulting structure, annealing the metal layer in an atmosphere comprising nitrogen, and removing any metal nitride regions. The local metal silicide interconnect structure may overlie the at least one gate structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 09/795,746,filed Feb. 28, 2001, pending, which is a divisional of application Ser.No. 09/291,762, filed Apr. 14, 1999, now U.S. Pat. No. 6,429,124, issuedAug. 6, 2002.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to the field of integrated circuitdesign and fabrication. Specifically, the invention relates to methodsfor making local interconnect structures for integrated circuits and thestructures formed thereby.

2. Background of Related Art

Integrated circuits (ICs) contain individual active and passive deviceswhich are interconnected during fabrication by an intricate network ofconductive material. The quality of these inter-device interconnectionsoften affects the performance and reliability of the overall IC device.

Local interconnects, unlike other interconnects such as multi-levelinterconnects, electrically connect the individual devices of theoverall IC device at a level or levels below customary metallizationlevels. For example, local interconnects connect gates and emitters todiffusion areas and N+ and P+ regions across field oxide regions. See T.Tang et al., Titanium Nitride Local Interconnect Technology for VLSI,IEEE Trans. Electron Devices, Vol. ED-34, 3 (1987) p. 682, thedisclosure of which is incorporated herein by reference.

Several materials have been employed in local interconnects, such astitanium nitride, refractory metals, and titanium silicide (TiSi_(x)).TiSi_(x) has been used frequently as a local interconnect materialbecause of its low resistance and high conductivity. Methods forfabricating local interconnects, such as TiSi_(x) local interconnects,include those described in U.S. Pat. Nos. 4,975,756, 5,589,415,5,605,853, and 5,612,243, the disclosures of which are incorporatedherein by reference.

U.S. Pat. No. 5,483,104, the disclosure of which is incorporated hereinby reference, discloses a method for fabricating TiSi_(x) localinterconnects. Silicided regions, which protect source and drain regionsfrom an overlying local interconnect, are formed by depositing titanium(Ti) on a silicon (Si) substrate and annealing the titanium to thesilicon in a nitrogen atmosphere. The local interconnect structure isthen formed on the silicide regions by depositing a doped polysiliconlayer, sputtering titanium on the polysilicon, and annealing in anitrogen atmosphere. Such a technique, however, often results in poorcontact between the silicided active area and the silicided localinterconnect if the polysilicon deposition is not very well controlled.

Another method for manufacturing TiSi_(x) local interconnects isdisclosed in U.S. Pat. No. 5,496,750 (“the '750 patent”), the disclosureof which is incorporated herein by reference. The '750 patent describesa method for fabricating elevated source/drain junction metal-on-siliconfield effect transistors (MOSFETs) extending from gate sidewalls toisolation structures surrounding the FET gate area. Unfortunately, themethod described in the '750 patent is limited because the methoddisclosed therein does not include the fabrication of a flexible localinterconnect structure.

Using titanium silicide as a local interconnect can result in severalproblems, as explained in U.S. Pat. No. 5,341,016, the disclosure ofwhich is incorporated herein by reference. One problem is that titaniumsilicide severely agglomerates when exposed to temperatures greater than850° C. Agglomeration can increase both silicided source/drain andpolycide sheet resistance and lead to excessive leakage and/or gateoxide degradation. Another problem with titanium silicide is unwanteddopant segregation, which can reduce the minority carrier lifetimeduring device operation and cause contact resistance problems.

A particular problem with TiSi_(x) local interconnects has been poorstep coverage. Conventionally, in forming the local interconnect, Ti hasbeen deposited first, followed by physical vapor deposition (PVD) ofsilicon. PVD silicon, however, suffers from poor step coverage. Thispoor step coverage often detracts from the quality of the semiconductordevice.

SUMMARY OF THE INVENTION

The present invention relates to a method for selectively fabricating aflexible metal silicide local interconnect over gates or otherstructures of a semiconductor device. The method of the presentinvention includes forming at least one gate structure on a substrate,disposing an amorphous or polycrystalline silicon layer on thesubstrate, disposing a layer of silicon nitride (SiN) over the siliconlayer, removing a portion of the silicon nitride layer, oxidizing theexposed portion of the silicon layer, removing the remaining portion ofthe silicon nitride layer, optionally removing the oxidized siliconlayer, forming a metal layer over the resulting structure, annealing themetal layer in an atmosphere comprising nitrogen, and removing any metalnitride regions. Preferably, the silicon layer is formed on thesubstrate and the at least one gate structure. In removing the portionof the silicon nitride layer, a remaining portion is preferably leftoverlying the at least one gate structure. More preferably, the methodleaves a local interconnect layer overlying the at least one gatestructure.

The present invention provides at least one advantage when compared toconventional local interconnect fabrication methods, in that the presentinvention forms TiSi_(x) local interconnects with good step coveragebecause the silicon forming the interconnects is deposited via chemicalvapor deposition (CVD).

Other features and advantages of the present invention will becomeapparent to those of skill in the art through consideration of theensuing description, the accompanying drawings, and the appended claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Certain aspects of the present invention are illustrated by theaccompanying drawings in which:

FIGS. 1-9 illustrate cross-sectional views of a process of forming localinterconnects, and the resulting structure, according to the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

This invention provides a flexible metal silicide local interconnect forintegrated circuit and semiconductor devices. In particular, the presentinvention provides a process for forming a flexible local interconnectstructure. As used in the context of the present invention, the term“flexible” means that the method of the present invention can beemployed to make a local interconnect structure that contacts anydesired active device region, or active region, of the semiconductordevice and that traverses over gates or other structures of thesemiconductor device.

The local interconnects of the present invention can be used in CMOSlogic devices and are especially suitable for SRAM devices. The localinterconnects and methods of fabrication described below exemplify theinventive process and structure in a CMOS logic device. However, theinventive process and structure as disclosed may be modified to beincluded in any desired device.

The following description provides specific details, such as materialthicknesses and types, in order to provide a thorough understanding ofthe present invention. The skilled artisan, however, will understandthat the present invention may be practiced without employing thesespecific details. Indeed, the present invention can be practiced inconjunction with fabrication techniques conventionally used in theindustry.

The process steps and structures described below do not form a completeprocess flow for manufacturing IC devices, the remainder of which isknown to those of ordinary skill in the art. Accordingly, only theprocess steps and structures necessary to understand the presentinvention are described.

As shown in FIG. 1, device isolation regions 4 are first formed insubstrate 2. Substrate 2 may be any surface suitable for deviceformation, such as a semiconductor wafer, and may be doped and/orinclude an epitaxial layer. Preferably, substrate 2 is a silicon waferor a bulk silicon region, such as a silicon-on-insulator orsilicon-on-sapphire structure. Impurities comprising atoms of oneconductivity type (e.g., P-type) may optionally be incorporated into thesubstrate. Device isolation regions 4 are illustrated in FIG. 1 as fieldoxide regions, but the present invention can be practiced using otherisolation technologies, such as trench-and-refill isolation regions.

A thin dielectric layer is then formed over substrate 2. This dielectriclayer comprises any dielectric material used in semiconductor devicefabrication. Examples of such dielectric materials include siliconoxide, silicon nitride, silicon oxynitride, silicon oxide containingdopants such as B or P, organic dielectrics, or a layered dielectricfilm of these materials. Preferably, this dielectric layer is siliconoxide. This dielectric layer may be formed by any suitable manufacturingmethod, such as a thermal reaction or vapor deposition process.

Next, a conductive layer is deposited. Since this conductive layer willform the gate electrode, any suitable gate electrode material may beemployed. Preferably, the conductive layer is a doped polysilicon layer.Optionally, a second dielectric layer is formed over this conductivelayer. This second dielectric layer may comprise any dielectric materialused in IC device fabrication, such as those listed above. This seconddielectric layer preferably comprises silicon oxide or silicon nitride.More preferably, this second dielectric layer is silicon oxide.

The conductive layer, dielectric layer, and second dielectric layer (ifpresent) are then patterned and etched, as illustrated in FIG. 1, toform gate structures 13 a, 13 b, and 13 c. The gate structures containgate dielectric 16, gate electrode 18, and, if desired, second gatedielectric 19. Gate structures 13 a, 13 b, and 13 c can be formed by anysuitable pattern and etch process, preferably using substrate 2 as anetch stop.

Sidewall dielectric spacers 20 on the gate structures are then formed.Spacers 20 may be formed by depositing a dielectric layer overall andetching the dielectric layer to leave substantially vertical sidewalldielectric spacers 20. Preferably, this dielectric layer comprisessilicon oxide or silicon nitride. More preferably, this dielectric layeris silicon oxide.

Diffusion regions 8, such as source/drain regions, are then formed insubstrate 2. Diffusion regions 8 can be formed by implanting a suitabledopant, such as B, As, or P, at an energy and dose sufficient,optionally through a dielectric layer, to form the desired dopantconcentration. Diffusion regions 8 may be created by ion implanting ahigh concentration of dopant atoms into substrate 2 to form dopedregions which are aligned to the edge of the dielectric spacers 20.Dielectric spacers 20 can optionally be removed and a second implantperformed to form doped regions which are aligned with the gatestructures. An optional diffusion step may be employed to drive in thedopants.

Gate contacts, if desired, are then formed. Gate contacts are formed byremoving a portion of second gate dielectric 19, if present, to exposethe gate electrode 18. This removal can be performed by patterning andetching the second gate dielectric. For example, the pattern and etchmay proceed by coating substrate 2 with a first photoresist to planarizethe wafer and then baking the first photoresist. The first photoresistis then blanket etched until second gate dielectric 19 is exposed. Anisolation mask is then used to isolate second gate dielectric 19. Anetch is then conducted to remove the desired portion of the second gatedielectric 19 and expose gate electrode 18, as shown with respect togate structure 13 c.

As shown in FIG. 2, a layer 25 of amorphous or polycrystalline siliconis deposited or otherwise formed on substrate 2 and gate structures 13a, 13 b and 13 c. Preferably, silicon layer 25 is polycrystallinesilicon (poly-silicon). The thickness of silicon layer 25 may range fromabout 300 to about 600 Å, and should be selected considering the devicecharacteristics and processing requirements. For example, the siliconlayer 25 thickness should be selected so that the TiSi_(x) or CoSi₂ orany other silicide interconnect forms through the original interfacebetween the deposited silicon and the underlying active areas.Preferably, the thickness of the layer of silicon facilitates thefabrication of a substantially confluent metal silicide layer. Siliconlayer 25 may be deposited by any IC device fabrication process yieldingthe desired chemical and physical characteristics, such as a highlyconformal or a partially conformal deposition process. Exemplaryprocesses include a PVD process, such as evaporation or sputtering, or aCVD process. Preferably, silicon layer 25 is deposited by any CVDprocess yielding good step coverage.

Silicon layer 25, especially when it is poly-silicon, may be optionallydoped. The dopant may be ion implanted at a dose and energy sufficientto obtain the desired concentration. Any dopant can be employed, such asAs, P, or B.

As illustrated in FIG. 3, silicon nitride layer 30 is then deposited orotherwise formed over silicon layer 25. Silicon nitride layer 30 can bedeposited by any fabrication method yielding the desired physical andchemical characteristics, such as a CVD or PVD process. Preferably,silicon nitride is deposited using a CVD low-pressure chemical vapordeposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).The thickness of the silicon nitride layer may range from about 100 Å toabout 400 Å, and should be selected considering the devicecharacteristics and processing requirements.

As depicted in FIG. 4, a portion of silicon nitride layer 30 is thenremoved, the portion of silicon nitride layer 30 remaining on siliconlayer 25 overlying those portions of the device on which the silicidelocal interconnect will be formed. Removal of portions of siliconnitride layer 30 is preferably performed by a photolithographicpatterning and etch process using photoresist layer 32, followed by adry etch of the silicon nitride.

As illustrated in FIG. 4, removing portions of silicon nitride layer 30will expose underlying regions of silicon layer 25. These exposedregions are then oxidized to form silicon oxide layer 35, as shown inFIG. 5, which is located at the same fabrication elevation, or level, asadjacent, remaining portions of silicon layer 25. Any oxidation processcan be employed to oxidize the exposed portions of silicon layer 25,provided it yields a silicon oxide layer 35 with the desired physicaland chemical characteristics. Preferably, the oxidation process isthermal oxidation in an atmosphere containing oxygen or steam at atemperature of from approximately 700° C. to 1000° C. for approximately1 to 30 minutes. Silicon nitride layer 30 serves as an oxidation maskand prevents undesired oxide growth on the portions of silicon layer 25covered thereby.

As shown in FIG. 6, the remaining portion of silicon nitride layer 30 isthen removed. Any removal process can be employed, provided it neitherremoves silicon oxide layer 35 nor degrades silicon layer 25. Thisremoval process can be accomplished using a plasma etch or wet stripchemistry using silicon layer 25 as an etch stop. Preferably, theremaining portions of silicon nitride layer 30 are removed using a wetetch solution comprising hot phosphoric acid.

Silicon oxide layer 35 can then be removed, if desired. Whether siliconoxide layer 35 is removed depends on whether the silicon regionsunderlying the silicon oxide layer 35 will be silicided. For example, asexplained below, if silicided diffusion regions 8 are not desired,silicon oxide layer 35 is not removed. Conversely, if silicideddiffusion regions 8 are desired, silicon oxide layer 35 is removed. Anysuitable fabrication process can be employed to remove the siliconoxide, provided it does not degrade either silicon layer 25 or siliconregions underlying silicon oxide layer 35. For example, this removalprocess can be accomplished using a plasma etch or wet strip chemistry.Preferably, the silicon oxide layer is removed using a wet etch solutioncomprising hydrofluoric acid (HF).

As shown in FIG. 7 a (in an embodiment where silicon oxide layer 35remains) and FIG. 7 b (in an embodiment where silicon oxide layer 35 hasbeen removed), metal layer 40 is deposited over the surface of thesemiconductor device. Metal layer 40 may be formed by any fabricationprocess imparting the necessary characteristics to the layer, such as aPVD or CVD process. Preferably, metal layer 40 is formed by a sputteringprocess, such as sputter deposition in an Ar atmosphere.

The metal layer may comprise any metal or material which forms asilicide when alloyed with silicon, such as a refractory metal.Preferably, the metal is Co, Ta, or Ti. More preferably, the refractorymetal layer is Ti. The thickness of the metal layer should beproportional to the thickness of the silicon layer. The thickness of thelayer of metal should be sufficient to substantially completely consumethe silicon as the metal and silicon are annealed. For example, if Ti isemployed as the metal, the thickness of the layer of Ti should be abouthalf of the thickness of the layer of silicon to substantiallycompletely consume the silicon layer. The thickness of the metal layershould also be sufficient to facilitate the fabrication of asubstantially confluent metal silicide layer during the annealing of themetal to the silicon. Preferably, the thickness should range from about200 to about 400 Å.

As depicted in FIG. 8 a (in an embodiment where silicon oxide layer 35remains) and FIG. 8 b (in an embodiment where silicon oxide layer 35 hasbeen removed), metal layer 40 is then converted to silicide interconnect45 and metal nitride layer 50. Preferably, this conversion is performedby annealing in a nitrogen-containing atmosphere. The annealinginitiates a chemical reaction between the metal layer and the underlyingsilicon and between the metal and the nitrogen ambient. A metal silicidelayer forms in the regions where the metal contacts silicon, therebyyielding silicide interconnect 45. Metal nitride layer 50 forms in theregions where the metal contacts an insulating or dielectric material.

The annealing process is performed in a nitrogen-containing atmospherefor a time and a temperature sufficient to react metal layer 40 andsilicon layer 25 and form a silicide; thus, silicide interconnect 45 islocated at substantially the same fabrication elevation, or level, asthat at which silicon layer 25 was previously located and, in FIG. 8 a,where silicon oxide layer 35 remains, at substantially the samefabrication elevation, or level, as silicon oxide layer 35. Preferably,the temperature ranges from about 600 to about 750° C. and the timeranges from about 20 seconds to about 10 minutes.

The nitrogen-containing atmosphere may comprise a gas or a mixture ofgases providing nitrogen for the annealing atmosphere, yet not adverselyinfluencing conversion of the metal layer. Examples of such gasesinclude nitrogen, ammonia, or a mixture thereof. Preferably, thenitrogen-containing atmosphere contains substantially pure nitrogen. Theannealing atmosphere may also contain other gases, such as argon orhydrogen.

This conversion process should proceed until a metal silicide formsthrough the original interface between silicon layer 25 and underlyingsubstrate 2. The time and temperature of the annealing process, as wellas the thickness of silicon layer 25, must therefore be selectedcarefully.

Metal nitride layer 50 is then removed to obtain the structures shown inFIG. 9 a (in an embodiment where silicon oxide layer 35 remains) andFIG. 9 b (in an embodiment where silicon oxide layer 35 has beenremoved). Any process for removing the metal nitride layer 50 withoutremoving or adversely affecting silicide interconnect 45 may beemployed. A wet etch solution containing H₂O, H₂O₂, and NH₄OH can beused to remove the metal nitride layer 50 without etching away thesilicide interconnect 45.

After removing the metal nitride layer 50, subsequent processing may beundertaken to form the desired semiconductor device. For example, a hightemperature anneal may be performed to reduce the silicide interconnectsheet resistivity. Additionally, a dielectric layer could be deposited,contact holes formed in the dielectric layer, and a patterned metallayer formed to achieve a desired pattern of electricalinterconnections.

While the preferred embodiments of the present invention have beendescribed above, the invention defined by the appended claims is not tobe limited by particular details set forth in the above description, asmany apparent variations thereof are possible without departing from thespirit or scope thereof.

1. A semiconductor device structure, comprising: at least one activedevice region; at least one transistor gate structure positionedlaterally adjacent to the at least one active device region; and aninterconnect comprising a layer including metal silicide and positionedto directly contact the at least one active device region; and a filmcomprising dielectric material at substantially the same fabricationlevel of the semiconductor device structure as the interconnect.
 2. Thesemiconductor device structure of claim 1, wherein the interconnect ispositioned to extend at least partially over the at least one transistorgate structure.
 3. The semiconductor device structure of claim 2,wherein the interconnect is also positioned to extend substantially overanother transistor gate structure of the semiconductor device structure.4. The semiconductor device structure of claim 1, wherein the metalsilicide comprises titanium silicide, tantalum silicide, or cobaltsilicide.
 5. The semiconductor device structure of claim 1, wherein themetal silicide comprises titanium silicide.
 6. The semiconductor devicestructure of claim 1, wherein the at least one active device regioncomprises an n-well.
 7. The semiconductor device structure of claim 1,wherein the film comprising dielectric material comprises a siliconoxide.
 8. The semiconductor device structure of claim 1, furthercomprising: a film comprising a metal nitride over at least portions ofthe film comprising dielectric material.
 9. A semiconductor devicestructure, comprising: a substrate comprising semiconductor material; atleast one structure positioned adjacent to an active surface of thesubstrate; an interconnect comprising a layer including metal silicidelocated over the active surface and adjacent to the at least onestructure; and a film comprising dielectric material at substantiallythe same fabrication level of the semiconductor device structure as theinterconnect.
 10. The semiconductor device structure of claim 9, furthercomprising: at least one active device region within the semiconductormaterial.
 11. The semiconductor device structure of claim 10, whereinthe interconnect contacts the at least one active device region.
 12. Thesemiconductor device structure of claim 10, wherein the at least oneactive device region comprises an n-well.
 13. The semiconductor devicestructure of claim 9, wherein the at least one structure comprises atransistor gate structure.
 14. The semiconductor device structure ofclaim 13, wherein the dielectric material comprises at least a side wallof the transistor gate structure.
 15. The semiconductor device structureof claim 9, wherein the dielectric material comprises at least one of asilicon oxide and a silicon nitride.
 16. The semiconductor devicestructure of claim 9, wherein the metal silicide comprises a refractorymetal silicide.
 17. The semiconductor device structure of claim 16,wherein the refractory metal silicide comprises titanium silicide,tantalum silicide, or cobalt silicide.
 18. The semiconductor devicestructure of claim 9, wherein the metal silicide comprises titaniumsilicide.
 19. The semiconductor device structure of claim 9, wherein atleast a portion of the interconnect is located adjacent to thedielectric material of the at least one structure.
 20. The semiconductordevice structure of claim 19, wherein the dielectric material of the atleast one structure comprises at least one of a silicon oxide and asilicon nitride.